Embodiments of the present disclosure relate generally to semiconductor packages and methods of manufacturing the same and, more particularly, to semiconductor packages including through electrodes and methods of manufacturing the same.
As demand for small-sized, high-performance and mobile electronic products have recently increased, ultra-small high-capacity semiconductor memory devices are correspondingly desired. In general, ways to increase the storage capacity of the semiconductor memory device include increasing the integration density of a semiconductor chip, or mounting and assembling a plurality of semiconductor chips within a single package. The former method may require much effort, cost, and time, while the latter packaging method may allow for easier ways to increase the storage capacity of the semiconductor memory devices. The latter method is advantageous in terms of costs, research, development effort, and development time, as compared to the former method. Hence, semiconductor memory manufacturers have made efforts to increase the storage capacity of the semiconductor memory device through a multi-chip package which mounts a plurality of semiconductor chips within a single semiconductor package.
A method of mounting the plurality of semiconductor chips within the single semiconductor package includes a method of mounting semiconductor chips horizontally or vertically. However, in order to contribute to smaller electronic products, most semiconductor memory manufacturers prefer a stack type multi-chip package in which semiconductor chips are stacked vertically. Most of the multi-chip stack packages may be realized using through silicon vias (TSVs) that penetrate semiconductor chips constituting the multi-chip packages.
In the semiconductor package in which semiconductor chips stacked using the TSVs are electrically connected, the TSVs penetrating the semiconductor chips may constitute electric connection paths. Thus, as the lengths of the electric connection paths decrease, large-capacity data may be advantageously processed at higher speeds. In the multi-chip stack package technology using TSVs, one of the most important steps is to form via holes penetrating semiconductor chips and to stack the semiconductor chips having TSVs at accurate positions. The TSVs may be formed by patterning the semiconductor chip to form via holes penetrating the semiconductor chip and by filling the via holes with a conductive material. That is, the via holes may be formed to completely penetrate a semiconductor chip from a first surface of the semiconductor chip to a second surface of the semiconductor chip opposite to the first surface. Thus, a depth of the via holes may be equal to a thickness of the semiconductor chip. However, it may be difficult to form deep via holes which may slow the development of the multi-chip stack packages. In addition, in the event that misalignment occurs between upper and lower TSVs in forming the multi-chip stack package by stacking a plurality of semiconductor chips having TSVs, an open failure may occur between the semiconductor chips.
Electronic elements constituting the semiconductor chip may be generally categorized as either active elements or passive elements. Active elements may operate in a non-linear characteristic region, and passive elements may operate in a linear characteristic region even if they exhibit both the non-linear characteristic region and the linear characteristic region. Active elements include transistors, and passive elements include capacitors, resistors, inductors, and so on. Passive elements may act as signal filters, and may be generally mounted on an arbitrary region such as a peripheral region of a package substrate on which a semiconductor package is mounted. However, passive elements mounted on the peripheral region of the package substrate may require additional area on a mother board and may considerably lower packing density of semiconductor packages.